1. Field of the Invention
The present invention relates to an image-processing module and the architecture thereof, particularly a module capable of synchronously operating a less time-consuming arithmetic and a more time-consuming arithmetic module, thereby reducing idle time and increasing hardware utilization, and the architecture thereof.
2. Description of the Prior Art
Given wider applicability of video, applications for video gradually increase. Consequently, the processing speed of video becomes very important. Nowadays, the one of widespread technologies for video is the Moving Picture Encoding Group (MPEG). Referring to FIG. 1, a conventional MPEG-4 video-encoding system consists of two parts: a motion estimator and a block encoder. The block encoder includes a motion-difference unit, a discrete cosine transform (DCT), a quantization unit, a variable length code (VLC), an inverse-quantization unit, an inverse discrete cosine transform (inverse DCT) and a motion-compensation unit. Given the motion estimator generates motion vectors, this involves a great number of arithmetic algorithms. It is known that computation of the motion estimator constitutes approximately 60˜70% of that of the entire encoding system.
Referring to FIG. 2, a prior art on video processing primarily involves the incorporation of an internal share memory into several functional independent arithmetic modules during video data processing, wherein the main arithmetic unit is taken as the motion estimator, and the secondary arithmetic unit is taken as the block encoder.
Referring to FIG. 3, taking images at a resolution of 704×576 as an example, video streams at respective resolutions of 704×576, 352×288 and 176×144 are generated at a time order of 0˜2. FIG. 3 shows that conventional video-processing modules can only process single-resolution data sequentially. In other words, when the main arithmetic unit is processing image data, the secondary arithmetic unit remains idle and the hardware utilization becomes very low. Consequently, when the conventional video-processing module is generating three different resolutions, operating cycles required for operations is 1.31×W×H×fps×A, where W is “width”; H is “height”; fps is “frame per second”; and A is the “operating cycles” of the main arithmetic unit. Referring to FIG. 4, in addition to low utilization of the secondary arithmetic unit, images of the same resolution should be subjected to the sequential operations of the main arithmetic unit and the secondary arithmetic unit before proceeding with the other resolution image processing.
Referring to FIG. 4, if the operating time of the main arithmetic unit is threefold that of the secondary arithmetic unit, the hardware utilization will worsen, thereby causing lower efficiency. The main reasons for low efficiency are:                (1) Given that the original internal share memory is expected to reduce bandwidth between external memory and system bus but the main arithmetic unit and the secondary arithmetic unit use the same share memory, the secondary arithmetic unit is unable to use the share memory concurrently when the main arithmetic unit is using it.        (2) When the main arithmetic unit and the secondary arithmetic unit differ greatly in their operating cycles.        (3) The secondary arithmetic unit must wait for the operating results of the main arithmetic unit before starting the next operation.        Given the above (1) to (3), during overall process period, the main arithmetic unit and the secondary arithmetic unit are sequential process one by one, causing large amount of the idle time.        
Referring to FIG. 5, when the video-processing module is processing videos from three different video devices and generating multiple-resolution video streams corresponding to multiple channels, the video-processing module will create considerable idle time, which reduces hardware utilization, wastes resources and lowers data-processing speed.
Conventional architecture causes serious wastage of hardware resources and affects data processing speed. Particularly with the gradual availability of Internet services nowadays, there are different video resolution requirements to accommodate to various demands. For example, a mobile telephone requires a resolution of 176×144; a personal digital assistant (PDA) requires a resolution of 176×144˜352×288; a personal computer requires a resolution of 352×288˜640×480; and a database requires a resolution of 640×480˜1024×768. Given many electronic devices require multiple-channel video data processing and real-time generation of multiple-resolution video streams to be transmitted to a remote end. Unfortunately, the drawbacks inherent in the prior art cause a bottleneck in data processing, making higher service quality impossible.